The objective of this report is to design a parallel 4-bit adder for low power consumption using 0.18 micron technology. The transmission gate implementation of the 4-bit ripple carry adder is chosen. Implementation is based on a bottom-up design methodology from schematic design of individual devices to integration. Critical paths are abstracted and optimized for low power dissipation. The schematic design is translated into prefabrication layout. Simulation of the schematic and layout realizations of the adder is performed and results are discussed. Performance is validated with specifications imposed by the target application.

E&CE437 Project

0.18 Micron 4-bit Transmission Gate Ripple Carry Adder for Low Power Consumption Design

The purpose of this project was to explore the digital design process through VHDL and the implementation of a high performance, 16-instruction, 16-bit, microprocessor called the TOY CPU on an APEX 20K200EFC484-2X FPGA. The goal for this design was to maximize operating frequency while minimizing the total number of logic elements and clock cycles.

E&CE427 Project

16-instruction 16-bit High Performance Microprocessor Design