The purpose of this project was to explore the digital design process through VHDL and the implementation of a high performance, 16-instruction, 16-bit, microprocessor called the TOY CPU on an APEX 20K200EFC484-2X FPGA. The goal for this design was to maximize operating frequency while minimizing the total number of logic elements and clock cycles.
Welcome to my new website! If you are reading this, you have been fortunate enough to stumble across a very early version of this site as it has yet to be populated with content and is still missing some functionality. However, rest assured there will be more to come in the following days… weeks as I gradually bulk load all of the content. As for now, this will mainly serve as a temporary front for my services.
Photo captured with my Leica M3 / Summicron 50mm / Ilford B&W Film
Welcome! Bienvenue!